1. Field of the Invention
The methods of the present invention relate to the fabrication of conducting vias and conducting lines for integrated circuits in semiconductor devices. More particularly, the methods of the present invention relate to the use of sacrificial inorganic dielectrics in dual damascene methods utilizing low dielectric constant organic intermetal dielectric layers.
2. Description of the Related Art
The desired characteristic feature size in integrated circuits continues to decrease. Conversely, the desired number of stacked metal interconnect and intermetal dielectric layers in integrated circuits continues to increase. These trends drive the development of new integrated circuit fabrication methods and the incorporation of new materials into integrated circuits.
In accord with these trends, damascene processes are replacing traditional subtractive etching methods as the primary metal patterning technique in integrated circuit fabrication. In traditional subtractive etching methods, a metal layer is deposited on a dielectric layer, and a photoresist layer is deposited on the metal layer. The photoresist is patterned photolithographically to correspond to the desired conductor pattern. The metal not protected by the photoresist is etched away to leave the desired conductor pattern.
In damascene methods, a pattern corresponding to the desired conductor pattern is etched into a dielectric layer. The etched pattern is filled with conductor to form the desired conductor pattern. In single damascene methods, deposition of conducting material into interconnect patterns and via patterns occurs in separate steps. In dual damascene methods, the interconnect and via patterns are filled simultaneously. Damascene methods provide reduced feature sizes compared to traditional subtractive etching methods. In addition, damascene methods can use copper as a conductor. Copper is difficult to use in subtractive processes. Dual damascene methods require fewer process steps than single damascene methods, and thus reduce fabrication costs. Dual damascene methods of integrated circuit fabrication are discussed, for example, in U.S. Pat. Nos. 5,635,423; 5,686,354; 5,705,430; and 5,795,823. Dual damascene methods include xe2x80x9cvia firstxe2x80x9d methods in which via openings are etched in a stack of dielectric layers before conducting line openings are etched, and xe2x80x9cline firstxe2x80x9d methods in which line openings are etched before via openings are etched.
The reduced feature size in integrated circuits provided by new fabrication techniques results, in principle, in improved device performance. However, capacitive coupling between conductors increases as the distance between conductors decreases. This capacitive coupling degrades device performance.
Capacitive coupling between conductors is proportional to the dielectric constant of the material separating the conductors. Consequently, the capacitive coupling between conductors in an integrated circuit can be reduced by reducing the dielectric constant of the intermetal dielectric layers in the integrated circuit. Thus, industry desires dual damascene processes incorporating low dielectric constant materials.
Many of the low dielectric constant materials being considered for use in dual damascene integrated circuit fabrication processes are organic materials. Examples of such low dielectric constant organic materials include polyimides, polytetrafluoroethylene, parylenes, fluorinated and non fluorinated poly(arylene ethers), for example the poly(arylene ether) available under the tradename FLARE(trademark) from Honeywell Inc., the polymeric material obtained from the phenyl-ethynylated aromatic monomer provided by Dow Chemical Company under the tradename SiLK(trademark), and fluorinated amorphous carbon.
Unfortunately, such organic low dielectric constant materials share many chemical properties with the typically organic photoresist and sacrificial (temporary) fill materials used in dual damascene processes. Consequently, organic intermetal dielectric layers are vulnerable to damage during the photoresist and sacrificial fill stripping steps of integrated circuit fabrication and thus difficult to incorporate into dual damascene processes.
Typical problems associated with incorporating organic intermetal dielectric layers into conventional dual darnascene processes occur, for example, in the portion of the process flow for a xe2x80x9cvia firstxe2x80x9d dual damascene scheme illustrated in FIGS. 1a-1d. FIG. 1a depicts a substrate, 100, overlaid by a stack of dielectric layers including a diffusion barrier, 101, an organic intermetal dielectric layer, 102, and an inorganic hardmask layer 103. In an earlier process step, not shown, a via opening, 104, was etched into hardmask layer, 103, and organic intermetal dielectric layer, 102.
As illustrated in FIG. 1b, the via opening, 104, is filled by sacrificial fill layer, 105, which also covers hardmask layer, 103. A photoresist layer, 106, is deposited on sacrificial fill layer 105, baked, photolithographically patterned with a mask defining a desired line opening, and developed. The sacrificial fill material is typically an organic material such as a conventional photoresist material, which may or may not absorb light of the wavelength used in the photolithographic process, or organic antireflective coating (ARC). The sacrificial fill material is typically thermally cross-linked to make it resistant to the 2.5% solution of tetramethylammoniumhydroxide (TMAH) typically used to develop photoresist layer, 106.
As illustrated in FIG. 1c, the portion of the sacrificial fill layer, 105, not covered by the photoresist layer, 106, is typically anisotropically etched with an oxygen based plasma to uncover a portion of inorganic hardmask layer, 103, and to reopen a portion of via opening, 104. The edges, 106a, of photoresist layer, 106, are typically rounded by the oxygen based plasma etch, which attacks the typically organic photoresist as well as the organic sacrificial material. Such rounding of the photoresist layer edges, 106a, can degrade critical dimensions in the interconnect pattern and lead to shorting and other electrical problems in the circuit.
The portion of inorganic hardmask layer, 103, uncovered by the etch of sacrificial fill layer, 105, is typically etched with an anisotropic fluorocarbon based plasma to uncover a portion of organic intermetal dielectric layer, 102. The portion of organic intermetal dielectric layer, 102, uncovered by the etch of hardmask layer, 103, is anisotropically etched with an oxygen based plasma to form line opening, 107, as depicted in FIG. 1d. The photoresist layer, 106, is also stripped by the oxygen based plasma during the etch of organic dielectric layer, 102.
The remaining sacrificial fill material, 105, must be stripped from via opening, 104, and from the surface of hardmask layer, 103, before via opening, 104, and line opening, 107, are filled with conductor. However, conventional organic sacrificial fill materials cannot be easily stripped without damaging organic intermetal dielectric layer, 102, or its adhesion to adjacent layers, and degrading critical dimensions of the interconnect pattern.
What is needed is a dual damascene process which incorporates organic dielectric intermetal layers and is not subject to the drawbacks of previous methods utilizing conventional organic sacrificial fill materials.
Dual damascene methods are presented in which developer resistant sacrificial inorganic dielectrics temporarily cover and fill openings in organic intermetal dielectric layers. Advantageously, the sacrificial inorganic dielectrics are selectively etched without damaging the organic intermetal layers. In one embodiment of the present invention, a via opening is formed in an organic intermetal dielectric layer. The via opening is filled with a sacrificial inorganic dielectric. A line opening is formed in the sacrificial inorganic dielectric and the organic intermetal dielectric layer. The line opening is formed substantially aligned with the via opening. The sacrificial inorganic dielectric is removed. The via opening and line opening are filled with a conducting material.
In a second embodiment of the present invention, a line opening is formed in an organic intermetal dielectric layer. The line opening is filled with a sacrificial inorganic dielectric. A via opening is formed in the sacrificial inorganic dielectric and the organic intermetal dielectric layer. The via opening is formed substantially aligned with the line opening. The sacrificial inorganic dielectric is removed. The via opening and line opening are filled with a conducting material.
The sacrificial inorganic dielectrics are typically etched with fluorocarbon based plasmas and stripped with a buffered oxide etch. In contrast, the organic intermetal dielectric layers and the organic photoresists are typically etched or stripped with an oxygen based plasma or with a reducing hydrogen based plasma such as an NH3 or N2+H2 based plasma.
The sacrificial inorganic dielectrics provide a flat surface onto which a thin uniform layer of photoresist is deposited. Photoresist layers may be stripped without damaging organic dielectric layers covered by sacrificial inorganic dielectrics, facilitating photoresist rework. The sacrificial inorganic dielectrics are etched without eroding photoresist patterns, thereby preserving critical dimensions. The sacrificial inorganic dielectrics are etched during inorganic hardmask layer and inorganic etchstop layer etches. Etching steps are thereby eliminated, compared to damascene processes utilizing conventional organic sacrificial fills.